AccelerComm IP is typically provided in the form of a netlist, which can be put onto an FPGA device or synthesized into an ASIC.
We provide acceptance test benches that make it easy to see how that interface works. We also have reference platforms, so where that IP needs integration with DDR memory, for example, or PCI express interfaces, we provide a reference platform that illustrates that already working in an example that you can build yourself.
We provide acceptance test benches that make it easy to see how that interface works. We also have reference platforms, so where that IP needs integration with DDR memory, for example, or PCI express interfaces, we provide a reference platform that illustrates that already working in an example that you can build yourself.
The AccelerComm IP has reconfigurable architectures with a number of different polars and parameters. These can be configured to suit the particular requirements of any particular application. So, if there's an application that demands a very low latency, we can turn up the polars and parameters, and get absolutely the best logic usage that meets that latency requirement.
Typically, if there's a different requirement, then the parameters might be optimized in a different way and we can configure that particularly for your needs.
We have MATLAB models that we make open source, which illustrate the operation of the standards. So we provide MATLAB in a way which is very closely aligned with the way that the standards are written, so that we can be absolutely sure that we have total conformance to those standards. And we also provide receiver models.
The standards only define the operation of the transmitter. So these receiver models allow our customers, and the people all around the world, to see how these standards really operate, both in the transmit side and the receive side.
AccelerComm takes a very comprehensive view, when it comes to verification of the IP. We have C models that accurately illustrate the operation of every piece of the IP. At the unit level, the core level, the chain level as well, and we can guarantee 100% match between the C model and the RTL.
We have very extensive test benches using UVM at the unit level and the chain level, to make sure that this conformity is guaranteed across all combinations of parameters and across all configurations of the IP as well.
We have produced data briefs that characterize the performance of the decoder across a wide variety of different scenarios.
These can be found within our downloads area.