In partnership with Xilinx
Introducing our productised PCIe acceleration card solution for Virtual RAN systems. In partnership with Xilinx, AccelerComm have developed a plug & Play PCIe Card with 5G optimised FPGA and software installation system based on open standard api’s.
Please contact us if you would like to arrange a live demonstration of our PCIe acceleration card solution.
We are seeing a movement in the telecommunications market that's driving standards so that the 5G supply chain can be more democratized and enable smaller companies to innovate with impact - such as doubling spectral efficiency.
Two examples of those standards are Open Radio Access Network (O-RAN) and virtual Radio Access Networks (vRAN) which offer cloud-like flexibility and automation capabilities that can optimize the RAN performance and ultimately improve the experience for users.
To address this infrastructure providers are accelerating the virtual functions using PCIe accelerator cards. Which can improve workloads by 45x over standard CPU implementations. Rob Barnes, CCO at AccelerComm
To enable flexible, configurable 5G networks both architecture types use virtual baseband functions that are highly compute intensive, especially for functions such as LDPC, which can take as much as 40% of the L1 processing.
To address this infrastructure providers are accelerating the virtual functions using PCIe accelerator cards. Which can improve workloads by 45x over standard CPU implementations.
Acceleration Market Trends
The market today is looking at different kinds of acceleration. But the difficulty is the lagging standards. Currently O-RAN working group 6 is defining an open standard API called AAL.
Traditional SoC companies are offering complete in-line PHY acceleration programmed onto a PCIe card which offloads the whole L1. This acceleration is known as the in line profile but the api definition is currently still under discussion within O-RAN.
A standard that is further ahead within O-RAN is using an api called BBDEV from the DPDK organization. This allows a Look-a-side accelerator solution, where the L1 is still largely running on a CPU but only the LDPC functions are passed to a generic PCIe card via the BBDEV api. This solution is available now and can be widely deployed by AccelerComm for Xilinx and Intel FPGA card solutions.
AccelerComm will continue to drive the standards and support improved performance and CPU offload as required by the market, including that of a complete in-line PHY profile.
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